1. Field of the Invention
The present invention relates to a false path detecting apparatus and a false path detecting method for detecting a false path implying a path that is not active in a combination of circuit operations, in circuits generated by behavioral synthesis, and a program for the same.
2. Description of the Related Art
Conventionally, as a technique used to design a large logical circuit, there is a behavioral synthesizing technique of automatically generating an RTL (Register Transfer Level) circuit, on the basis of a behavior description describing only a behavior, which does not contain a structure of hard-ware. Moreover, there is a logically synthesizing technique of converting this RTL circuit into a net list of a gate level. As for the circuit generated at this time, the circuit is generated under a predetermined delay constraint so that the delays of all paths (routes of data) are in a range of a predetermined period. At this time, in particular, in a circuit having a state transition and the like, there is a combination path of nets that do not become active at the same time throughout all the states. This path is a false path. The final false path is determined by the combination of paths that become active in each other states (hereafter, referred to as a true path).
If the logically synthesizing circuit satisfies only the delay constraint of the true path, the circuit is normally operated even if the delay of the false path is at the longest. So, the information with regard to the true path and the false path is reflected in the logical synthesis, and the delay constraint is not performed on the false path. At this time, as a method of extracting the information with regard to the true path and the false path from the circuit information after the behavioral synthesis, there is a method of checking the true path or the false path by referring to the information of the true path and comparing it, for the patterns of all the paths of the circuit. The false path detecting apparatus using the method will be described below with reference to the drawings.
FIG. 1 is a view showing a conventional false path detecting apparatus. A false path detecting apparatus 3 receives a circuit information outputted by a behavioral synthesizing system 1, a data flow information and a resource assignment information through a memory 4, and carries out a process as described below, and then outputs a false path information.
A true path lister 31 extracts all the true paths in the circuit from the circuit information, the data flow information and the resource assignment information, and stores them in a true path memory 34. For all partial circuits shared by an operating unit in partial circuits constituted by any combination in the true path memory 34, a false path candidate generator 32 extracts all paths existing in the partial circuit except the true path constituting the partial circuit, and outputs them to a false path minimizing device 33. The false path minimizing device 33 shortens the path from both the ends thereof while checking that the false path candidate is not the true path, for all the false path candidates. Then, it outputs the shortest false path, which does not contain a redundant path, to an output device 2.
As mentioned above, conventionally, the information with regard to all the true paths is stored, which results in a problem that a large number of memories are required in a case of a circuit information of a large integrated circuit. Also, in order to attain the minimization of the false path candidate, the comparison with the true path is repeated, which results in a problem that it takes a long time to complete the process. Also, it is sure that the size of an integrated circuit is further increased in future. Depending on a case, this results in a problem that it can not be applied to a further large circuit because of the lack of memories, the process time which can not be within a process time durable for practical use and other reasons.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a false path detecting apparatus and a false path detecting method in which a usage amount of memories is smaller and a process is carried out at a higher speed, and that program.
In order to achieve an aspect of the present invention, a false path detecting method, includes: (a) providing a data flow occurrence condition that a net becomes active, with regard to each of a plurality of nets; (b) selecting one of the plurality of nets as a selected net; (c) selecting, as a first specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the selected net of the plurality of nets; (d) adding the first specific net to the selected net to generate a first specific path; and (e) judging whether or not the first specific path is a false path based on the data flow occurrence condition of the selected net and the data flow occurrence condition of the first specific net.
In this case, the false path detecting method further includes: (f) selecting, as a second specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the first specific path of the plurality of nets, when in the (e) the first specific path is not a false path; (g) adding the second specific net to the first specific path to generate a second specific path; and (h) judging whether or not the second specific path is a false path based on the data flow occurrence condition of the first specific path and the data flow occurrence condition of the second specific net.
Also in this case, a circuit including the false path can be designed without consideration of a delay time of the false path.
Further in this case, the data flow occurrence condition is represented as an identifier or an OR operation of identifiers.
In this case, whether or not the first specific path is the false path depends on a comparison of the identifier of the data flow occurrence condition of the selected net to the identifier of the data flow occurrence condition of the first specific net.
Also in this case, the first specific path is the false path when a result of an AND operation between the identifier of the data flow occurrence condition of the selected net and the identifier of the data flow occurrence condition of the first specific net corresponds to xe2x80x9c0xe2x80x9d.
Further in this case, when the element connected to the input side or the output side of the selected net is an input terminal, an output terminal or a memory element, the (c), (d) and (e) are not performed.
In this case, the data flow occurrence condition is provided by an behavioral synthesis of automatically generating an RTL (Register Transfer Level) circuit based on a behavior description describing only a behavior, which does not contain a structure of hard-ware.
Also in this case, the false path detecting method is performed when the behavioral synthesis is performed.
Further in this case, the false path detecting method further includes: (i) judging whether or not the false path includes a redundant net; and (j) outputting the false path other than the false path including the redundant net.
In this case, the data flow occurrence condition is represented as an identifier or an OR operation of identifiers, and in the (i), when an AND operation with regard to the plurality of identifiers of the plurality of nets of the false path in order of an input side or an output side of the false path is performed until a result of the AND operation corresponds to xe2x80x9c0xe2x80x9d and the net on which the AND operation is not yet performed remains in case of the result corresponding to the xe2x80x9c0xe2x80x9d, the false path is judged to include the redundant net of the remaining net.
In order to achieve another aspect of the present invention, a false path detecting apparatus, includes: an active condition extracting processor extracting a data flow occurrence condition that a net becomes active, with regard to each of a plurality of nets; a circuit information database storing the data flow occurrence conditions of the plurality of nets; a false path retrieving processor selects one of the plurality of nets as a selected net, and selects, as a first specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the selected net of the plurality of nets, and adds the first specific net to the selected net to generate a first specific path and judges whether or not the first specific path is a false path based on the data flow occurrence condition of the selected net and the data flow occurrence condition of the first specific net.
In this case, a circuit including the false path can be designed without consideration of a delay time of the false path.
Also in this case, the active condition extracting processor represents the data flow occurrence condition as an identifier or an OR operation of identifiers.
Further in this case, whether or not the first specific path is the false path depends on a comparison of the identifier of the data flow occurrence condition of the selected net to the identifier of the data flow occurrence condition of the first specific net.
In this case, the first specific path is the false path when a result of an AND operation between the identifier of the data flow occurrence condition of the selected net and the identifier of the data flow occurrence condition of the first specific net corresponds to xe2x80x9c0xe2x80x9d.
Also in this case, when the element connected to the input side of the selected net is an input terminal, an output terminal or a memory element, the false path retrieving processor does not select the first specific net.
Further in this case, the active condition extracting processor extracts the data flow occurrence condition from a result of a behavioral synthesis of automatically generating an RTL (Register Transfer Level) circuit based on a behavior description describing only a behavior, which does not contain a structure of hard-ware.
In this case, the false path retrieving processor judges whether or not the first specific path is the false path when the behavioral synthesis is performed.
Also in this case, the false path detecting apparatus further includes: a redundant false path removing processor judging whether or not the false path includes a redundant net to output the false path other than the false path including the redundant net.
Further in this case, the data flow occurrence condition is represented as an identifier or an OR operation of identifiers, and when an AND operation with regard to the plurality of identifiers of the plurality of nets of the false path in order of an input side or an output side of the false path is performed until a result of the AND operation corresponds to xe2x80x9c0xe2x80x9d and the net on which the AND operation is not yet performed remains in case of the result corresponding to the xe2x80x9c0xe2x80x9d, the redundant false path removing processor judges the false path to include the redundant net of the remaining net.
In order to achieve still another aspect of the present invention, a program for a process, includes: (aa) providing a data flow occurrence condition that a net becomes active, with regard to each of a plurality of nets; (ab) selecting one of the plurality of nets as a selected net; (ac) selecting, as a first specific net, a net connected to an input side or an output side of an element connected to an input side or an output side of the selected net of the plurality of nets; (ad) adding the first specific net to the selected net to generate a first specific path; and (ae) judging whether or not the first specific path is a false path based on the data flow occurrence condition of the selected net and the data flow occurrence condition of the first specific net.
In this case, a circuit including the false path can be designed without consideration of a delay time of the false path.
The present invention is proposed in order to solve the above-mentioned problems. The false path detecting apparatus according to the present invention is provided with: an active condition extractor for extracting the condition information that each of the nets in a circuit becomes active on the basis of a circuit information implying an information with regard to a circuit generated by an behavioral synthesis, a data flow information indicative of a flow of a data on the circuit, and an assignment information of a function element constituting the circuit; a circuit information with an active condition database, in which the condition information is stored while correlated to the circuit information for each net; and a false path retriever for retrieving a false path implying a path, which does not become active in a combination of circuit operations, for each net, by referring to the circuit information with the active condition database.
Thus, it is provided with: the active condition extractor for extracting the condition information that each of the nets in the circuit becomes active on the basis of the circuit information implying the information with regard to the circuit generated by the behavioral synthesis, the data flow information indicative of the flow of the data on the circuit, and the assignment information of the function element constituting the circuit; the circuit information with the active condition database, in which the condition information is stored while correlated to the circuit information for each net; and the false path retriever for retrieving the false path implying the path, which does not become active in the combination of the circuit operations, for each net, by referring to the circuit information with the active condition database.
Also, in the false path detecting apparatus according to the present invention, the false path retriever refers to the circuit information with the active condition database, for the path having one or a plurality of nets, and thereby carries out the logical product between the conditions that the plurality of nets become active. Thus, it is characterized to judge whether or not the path is active.
Thus, the false path retriever refers to the circuit information with the active condition database, for the path including one or a plurality of nets, and then carries out the logical product between the conditions that the plurality of nets become active, and then judges whether or not the path is active. Hence, it is possible to easily judge whether or not the path having the plurality of continuous nets is the active path.
Also, the false path detecting apparatus according to the present invention further includes: an active path memory for storing therein an active path information implying an information with regard to a path that is active or a net; and a net information memory for storing therein a net information with regard to a net targeted for a process for retrieving a false path. The false path retriever stores all the nets of the circuit in the active path memory, reads out any one of the active paths or the nets stored in the active path memory, and judges whether an element at an end on an input side of the read out net or active path is an input terminal or a memory element. Then, if the element is neither input terminal nor memory element, it determines the net connected to the input side of the element whose output is the net or the active path, on the basis of the circuit information, stores the net information in the net information memory, reads out any one of the nets stored in the net information memory, generates a new path composed of the read out net and the active path or net read out from the active path memory, refers to the circuit information with the active condition database, for all the nets in the new path, carries out the logical product with regard to the condition that it becomes active, and judges whether or not the new path is active. Then, if the new path is active, it stores the new path as the active path information in the active path memory, and if the new path is not active, it outputs the new path as the false path.
Thus, the false path retriever reads out any one of the active paths or the nets stored in the active path information memory, determines the net connected to the input side of the element whose output is the net or the active path, on the basis of the circuit information, stores the net information in the net information memory, reads out any one of the nets stored in the net information memory, generates the new path composed of the read out net and the active path or net read out from the active path memory, carries out the logical product with regard to the condition that it becomes active, for all the nets in the new path, and judges whether or not the new path is active. Then, if the new path is not active, the false path retriever outputs the new path as the false path. Hence, whether or not it is the false path can be checked by investigating the net retroactively to the input side.
Also, the false path detecting method according to the present invention includes: a first step of extracting the condition information that each of the nets of the circuit becomes active, on the basis of a circuit information implying an information with regard to a circuit generated by an behavioral synthesis, a data flow information indicative of a flow of a data on the circuit and an assignment information of a function element constituting the circuit; and a second step of referring to a circuit information with an active condition database, in which the condition information is stored while correlated to the circuit information for each net, and then retrieving a false path implying a path that does not become active in the combination of circuit operations, for each net.
Also, in the false path detecting method according to the present invention, the second step refers to the circuit information with the active condition database, for the path having one or a plurality of nets, and thereby carries out the logical product between conditions that the plurality of nets become active. Thus, it is characterized to judge whether or not the path is active.
Also, in the false path detecting method according to the present invention, at the second step, it stores all the nets of the circuit in the active path memory, reads out any one of the active paths or the nets stored in the active path memory, and judges whether an element at an end on an input side of the read out net or active path is an input terminal or a memory element. Then, if the element is neither input terminal nor memory element, it determines the net connected to the input side of the element whose output is the net or the active path, on the basis of the circuit information, stores the net information in the net information memory, reads out any one of the nets stored in the net information memory, generates a new path composed of the read out net and the active path or net read out from the active path memory, refers to the circuit information with the active condition database, for all the nets in the new path, carries out the logical product with regard to the condition that it becomes active, and judges whether or not the new path is active. Then, if the new path is active, it stores the new path as the active path information in the active path memory, and if the new path is not active, it outputs the new path as the false path.
Also, the program according to the present invention is the program for instructing a computer to execute a first step of extracting the condition information that each of the nets in the circuit becomes active on the basis of the circuit information implying the information with regard to the circuit generated by the behavioral synthesis, the data flow information indicative of the flow of the data on the circuit, and the assignment information of the function element constituting the circuit; and a second step of referring to the circuit information with the active condition database, in which the condition information is stored while correlated to the circuit information for each net, and then retrieving the false path implying the path, which does not become active in the combination of the circuit operations, for each net.
Also, the program according to the present invention is the program for instructing the computer to further execute the second step of referring to the circuit information with the active condition database, for the path having one or a plurality of nets, and carrying out the logical product between the conditions that the plurality of nets become active, and then judging whether or not the path is active.
Also, the program according to the present invention is the program for instructing the computer to further execute the second step of storing all the nets of the circuit in the active path memory, reading out any one of the active paths or the nets stored in the active path memory, judging whether an element at an end on an input side of the read out net or active path is an input terminal or a memory element, and determining the net connected to the input side of the element whose output is the net or the active path, on the basis of the circuit information, if the element is neither input terminal nor memory element, and then storing the net information in the net information memory, reading out any one of the nets stored in the net information memory, generating a new path composed of the read out net and the active path or net read out from the active path memory, referring to the circuit information with the active condition database, for all the nets in the new path, carrying out the logical product with regard to the condition that it becomes active, judging whether or not the new path is active, and storing the new path as the active path information in the active path memory if the new path is active, and outputting the new path as the false path if the new path is not active, and outputting the new path as the false path if the new path is not active.